1. Field of the Invention
The present invention relates to an information processing apparatus containing a pipeline structure constituted of a multiprocessor system including first-in first-out (FIFO) buffers, each of the buffers being arranged between one processor and another processor thereof, and to an inter-processor communication control method.
2. Description of the Related Art
Recently, raster image processing methods for a color image processing apparatus have become more and more complicated. As a unit which executes a complicated algorithm rapidly with a high quality secured, a system including a pipeline system realized with multiprocessors has been proposed.
In the case of constructing the multiprocessors into a pipeline system, a method which accelerates memory access by disposing each of FIFO buffers between one processor and another one has been known.
A time required for sending a command to an FIFO buffer varies depending on processing time of each processor. If a difference of the time required for sending the command between processors is too large, an FIFO buffer located between one processor and another becomes full of stored data, so that the processor stalls, disabling sending of data. On the other hand, if a processor located in the downstream stage ends its processing too early, the processor cannot receive a command from a processor located in the upstream stage, so that it stalls. Although, to cope with these problems, the capacity of the FIFO buffer may be adjusted into an appropriate size through an operating analysis using a tremendous amount of data at the time of system design, a tremendous amount of work must be done for the operating analysis.
To achieve the pipeline system for the multiprocessors to meet these factors, it is necessary to eliminate a stall of the processor originating from a full storage of the buffer. Japanese Patent Application Laid-Open No. 2001-256200 discusses a method for a system including the FIFO buffer connecting the pipeline and a shared memory having a large latency, the method intending to detect that the FIFO buffer is full and to cause a processor in the upstream stage to transfer a command to the shared memory so that another processor in the downstream stage can access the shared memory to read out the command from the memory.
Japanese Patent Application Laid-Open No. 6-348644 discusses another method which, in direct memory access (DMA) control not through any processor (central processing unit (CPU)), processes data transmission in a short time by deleting data not necessary to transfer.
However, according to the data transfer technology discussed in Japanese Patent Application Laid-Open No. 2001-256200, the processor in the downstream stage needs to access a memory with a large latency to which the command has been transferred, and consequently, the effect of arranging the FIFO buffer between the processors drops remarkably.
Further, according to the DMA control technology discussed in Japanese Patent Application Laid-Open No. 6-348644, it is necessary to compare the content of the transfer data with the data which is preliminarily set and not required to transfer, and consequently, the DMA control unit cannot be constructed at a low cost.